A phase change memory element is a memory element for storing information using the characteristics of electric conductivity or a resistance difference between a crystalline phase and an amorphous phase of a specific phase change material. The phase change memory element forms a memory cell electrically connected to a transistor element or the like, formed on a semiconductor substrate for addressing and read/write operations of the device. In the memory element, information is stored using a conductivity difference in accordance with the phase change of a memory layer, and data is stored in the phase change memory element including a phase change region.
The phase change memory cell operates such that a current flowing through a transistor electrically heats a phase change region, and the structure of the phase change material is reversibly changed to a crystalline state or an amorphous state to store information. The stored information can be read by flowing a relatively low current through the phase change region and measuring the resistance of the phase change material.
In the formation of such a phase change memory element, one technical problem may be that power consumption may be excessively large because a phase change material may be required to be heated higher than its melting point for a write operation, particularly, a reset operation for changing a crystalline structure to an amorphous structure. Furthermore, another problem may result from the transistor element for operating the phase change memory element becoming smaller in size. In such a case, the power transferred to the phase change memory element through the transistor element may decrease.
In order to provide low power operation of the phase change memory element, the volume of the phase change region should be substantially minimized and the phase change region thermally insulated from its peripheral regions. Therefore, various types of device structures have been introduced for the low power operation of the phase change memory element, but there still exist many restrictions in the processes of fabricating semiconductor devices including the phase change memory elements. Particularly, with the high integration of phase change memory cell elements, many problems have been reported on the limits of a photo etching process for pattern formation and process restrictions related to an etch selectivity generated in the pattern formation.